Conductive metal lines at different elevations are typically formed in the fabrication of integrated circuitry. Each of these metal lines typically is connected to circuitry elevationally lower in the substrate by fabrication of via/contact openings into and through interlevel dielectric layers to different conductive nodes therebeneath. Accordingly, separate masks are typically utilized to fabricate the contact opening pattern for each elevation or level at which different metal lines are formed.
Semiconductor processing in the fabrication of integrated circuitry strives to reduce the number of processing steps a wafer is subjected to, and especially the number of masking steps. This can reduce the overall cost of manufacturing and as well reduces risk in damaging of the wafer by reducing the opportunity for damage.
While the invention was motivated in addressing the above issues and improving upon the above-described drawbacks, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded (without interpretative or other limiting reference to the above background art description, remaining portions of the specification, or the drawings), and in accordance with the doctrine of equivalents.